Hermetic seal and reliable bonding structures for 3d applications

ABSTRACT

A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it&#39;s perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

This invention was made with Government support under Contract No.N66001-00-C-8003 and N66001-04-C-8032 awarded by Defense. AdvancedResearch Projects Agency (DARPA). The Government has certain rights inthis invention.

FIELD OF THE INVENTION

The present invention relates to a sealed semiconductor structure usinga bonding technique and, more specifically, relates to a bonded sealedsemiconductor structure including structural support elements.

BACKGROUND OF THE INVENTION

Integrated circuits (ICs) form the basis for many electronic systems.Essentially, an integrated circuit (IC) or chip includes a vast numberof transistors and other circuit elements that are formed on a singlesemiconductor wafer and are interconnected to implement a desiredfunction. The complexity of these integrated circuits (ICs) requires theuse of an increasing number of linked transistors and other circuitelements.

Many modern electronic systems are created through the use of a varietyof different integrated circuits, where each integrated circuit (IC orchip) performs one or more specific functions. For example, computersystems include at least one microprocessor and a number of memorychips. Conventionally, each of these integrated circuits (ICs) areformed on a separate chip, packaged independently and interconnected on,for example, a printed circuit board (PCB).

In micoelectronics, a wafer is a thin slice of semiconducting material,such as a silicon crystal, upon which microcircuits are constructed forexample, by doping, etching, or deposition. Wafers are used in thefabrication of semiconductor devices such as integrated circuits orchips or dies. A single wafer may have a plurality of chips formed onthe wafer. The wafer may be used having a plurality of chips formedtherein, or the wafer may be cut to provide individual dies or chips.The wafers and chips or dies can form a stack by positioning the wafersand/or chips on top of one another. Copper bonding (Cu bonding)processes can be used to stack dies/chips at a chip-to-chip,chip-to-wafer, or wafer-to-wafer level.

As integrated circuit (IC) technology progresses, a need for a “systemon a chip” in which the functionality of all of the IC devices of thesystem are packaged together without a conventional printed circuitboard (PCB). Ideally, a computing system should be fabricated with allthe necessary IC devices on a single chip. In practice, however, it isvery difficult to implement a truly high-performance “system on a chip”because of vastly different fabrication processes and differentmanufacturing yields for the logic and memory circuits.

As a compromise, various “system modules” have been introduced thatelectrically connect and package integrated circuit (IC) devices whichare fabricated on the same or on different semiconductor wafers.Initially, system modules have been created by simply stacking twochips, e.g., a logic and memory chip, on top of one another in anarrangement commonly referred to as chip-on-chip structure.Subsequently, multi-chip module (MCM) technology has been utilized tostack a number of chips on a common substrate to reduce the overall sizeand weight of the package which directly translates into reduced systemsize.

Existing multi-chip module (MCM) technology provides performanceenhancements over single chip or chip-on-chip (COC) packagingapproaches. For example, when several semiconductor chips are mountedand interconnected on a common substrate through very high densityinterconnects, higher silicon packaging density and shorter chip-to-chipinterconnections can be achieved. In addition, low dielectric constantmaterials and higher wiring density can also be obtained which lead toincreased system speed and reliability, reduced weight, volume, powerconsumption, and heat to be dissipated for the same level ofperformance. However, MCM approaches still suffer from additionalproblems, such as, bulky packaging, wire length and wire bonding thatgives rise to stray inductances which interfere with the operation ofthe system module.

Typically, optimization of Cu bonding was achieved by utilizing onepattern density with specific bond pad dimensions and/or via dimensions.Vias and electrically connected pads refer to vias/pads with a platedhole that connects conductive tracks from one layer of a chip to anotherlayer(s). Current solutions are not compatible with standard CMOSprocesses in which a variety of pattern densities and pad/via sizes maybe used. Additionally, due to mechanical stability issues most of thebonding fails occur at the edge of the bonded pattern which often, inaddition to degraded bonding yield, leads to corrosion issues.Additionally, for 3D applications, a method or device is needed toprovide additional protection from mechanical damage (such as crackpropagation, chipping, dicing, etc.) caused during the semiconductorfabrication process.

In the current state of the art, electrically active bonded pads and/orvias had to be often placed in the central location of the pattern toprovide good reliability for these contacts. One major challenge ofthree dimensional (3-D) wafer-to-wafer vertical stack integrationtechnology is the metal bonding between wafers and between die in asingle chip, and the wafer protection from possible corrosion andcontamination caused or generated by process steps after the wafers arebonded from reaching active IC devices on the bonded wafers.

Therefore, a need exists to erect a barrier structure by the edge ofbonded wafers and individual die to protect the bonded wafers and dieagainst corrosion and contamination in a three-dimensional (3-D)wafer-to-wafer vertical stack. It would also be desirable to provide animproved metal bonding method having acceptable bonding yield andreliability without being limited to pattern density or pad/viadimensions.

SUMMARY OF THE INVENTION

In an aspect of the invention, a sealed microelectronic structureproviding mechanical stress endurance is provided which comprises atleast two chips including and being electrically connected to asemiconductor structure and comprising outer edges. Each chip includes acontinuous length of bonding material on a planar surface area thereofdefining a perimeter in spaced adjacency to the outer edge. At least onesupport column is connected to each of the chips and positioned withinthe perimeter of each chip. Each support column extends outwardly suchthat when the at least two chips are positioned in overlapping relationto one another, opposing support columns mate with each other or with anopposing planar surface area on the overlapping chip. A seal between theat least two chips results from the at least two chips being positionedin overlapping relation to one another such that the bonding material oneach chip is in mating relation to each other whereby the seal is formedwhen the at least two chips are mated together resulting in a bondedchip structure.

In a related aspect of the invention, the bonding material on the atleast two chips is compressed and the bonding material is heated to formthe seal.

In another related aspect of the invention, a plurality of chips arepositioned on at least two wafers. The wafers each include a continuousbonding material along a perimeter substantially adjacent to an outeredge of the wafer. The at least two wafers are sealed together when thebonding material on each of the wafers is compressed on each other inmating relation and heated to form the seal.

In another related aspect of the invention, the chips are electricallyconnected to their respective substrates to form an electrical circuiton the chips and the support columns are non-electrical and thereby arenot part of the electrical circuit.

In another related aspect of the invention, the chips are electricallyconnected to their respective substrates and electrical connected totheir respective wafers to form an electrical circuit on the chips andthe wafers and the support columns are non-electric and thereby not partof the electrical circuit.

In another related aspect of the invention the chips have multiplelayers and the support columns are positioned between the layers andadapted to provide support between the layers.

In an aspect of the present invention, a method for sealing amicroelectronic structure and providing mechanical stress endurancecomprises providing at least two chips including and being electricallyconnected to a semiconductor structure at a plurality of locations. Alength of continuous bonding material is deposited on each chip on aplanar surface thereof defining a perimeter substantially adjacent tothe outer edge. At least one support column is connected on each of thechips and within the perimeter of each chip, and each support columnextends outwardly. The chips are positioned in overlapping relation suchthat the bonding material and the support columns are in mating relationto each other. The chips are compressed and thereby the bonding materialis also compressed together. The bonding material is heated to form aseal about the perimeter of the chips whereby a bonded chip structure isformed.

In a related aspect of the invention, a plurality of chips arepositioned on at least two wafers, and a bonding material is depositedalong a perimeter adjacent to an outer edge of the wafer. The bondingmaterial is compressed on each of the wafers together with each other inmating relation. The mated bonding material is heated to form a seal,thereby forming a bonded wafers structure.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the presentinvention will become apparent from the following detailed descriptionof illustrative embodiments thereof, which is to be read in connectionwith the accompanying drawings, in which:

FIG. 1A is a block diagram according to an embodiment of the inventiondepicting a unbonded silicon wafers and Cu plated bond pads;

FIG. 1B is a block diagram of the silicon wafers and Cu plated bond padsshown in FIG. 1A bonded together;

FIG. 2 is plan view of a wafer including a plurality of chips withbonding material around the perimeter of the chips and the perimeter ofthe wafer;

FIGS. 3A and 3B is a plan view of two wafers depicting a bondingmaterial around their perimeters and having a plurality of bonding pads;

FIG. 3C is a cross sectional view of the wafers shown in FIGS. 3A and 3Bbonded together;

FIGS. 4A and 4B are a plan view of two wafers including a plurality ofchips wherein the wafers and the chips have bonding material on theirperimeters;

FIG. 4C is a perspective view of the wafers shown in FIGS. 4A and 4Bbonded together; and

FIG. 4D is a cross sectional view along line X-X of the bonded wafersshown in FIG. 4C.

DETAILED DESCRIPTION OF THE INVENTION

Generally, the present invention provides the ability to sealchip/structures/wafers which enables mechanical stability of criticaljoined components and protects from outside environmental damage. Thesealing procedure of the present invention for sealing stacked wafer orchips enables structures to be hermetically sealed at a chip/die leveland also allows wafer-level sealing which will enable downstreamfull-wafer processing. Furthermore, the sealing solution can also beutilized for electrical signal propagation and thermal dissipation or asa thermal conductor (through sealant material itself or using sealant asa thermal structure for dissipation). Materials that can be used to sealtogether chips or wafers include: metals (for example: Cu—Cu, Au—Au,etc.); alloys (such as: Cu—Sn, AuSn, etc.); solders; dielectrics(oxide-oxide); conductive adhesives (Cu-loaded pastes) and anycombination thereof (example indium-oxide).

More specifically, referring to FIG. 1A, for illustrative purposes, twosilicon wafers 10 are shown. A first silicon wafer 10 a is positionedover a second silicon wafer 10 b. Each silicon wafer may include aplurality of electrical elements fabricated using known semiconductorfabricating techniques on a top surface and/or in an upper layer of thewafer or a chip. Further, the electrical elements can be connected toeach other and to electrically conductive vias extending throughout thewafer or chip and/or a substrate portion of the wafer or chip formingmultiple circuits to provide, for example, power, connectivity, orcircuit logic. The first silicon wafer 10 a includes a silicon layer 14a and an oxide layer 18 a. Similarly, the second silicon wafer 10 bincludes a silicon layer 14 b and an oxide layer 10 b, in mirror imagerelationship to the first silicon wafer 10 a. Further, the first siliconwafer 10 a includes a copper (Cu) plated bond pad 22 a, and the secondsilicon wafer 10 b also includes a copper (Cu) plated bond pad 22 b. Thebond pads 22 a and 22 b are positioned in mating relationship to eachother.

Referring to FIG. 1B, the first silicon wafer 10 a and second siliconwafer 10 b are bonded together at a bonded area 26 using the copperplated bond pads 22 a, 22 b of silicon layers 14 a, 14 b. The bondedarea 26 formed by compressing the first and second silicon wafer 10, 10b together. Heat is also applied to the bonded area 26 to form the bondand seal the wafers 10 a, 10 b together. Thus, the first and secondsilicon wafers 10 a, 10 b are positioned in mating relation, as shown inFIG. 1A, and the Cu plated bonding pads 22 a, 22 b are mated togetherand sealed by using compression and heat. The bonded structure ispreferably hermetically sealed, i.e., an airtight seal, which isintended to secure against the entry of unwanted particles and elementsto maintain the quality of the electrical components and circuitry inthe bonded structure. Other material may be used other than cooper toaccomplish the sealing bond. Further, the seal prevents corrosion fromatmosphere (humidity or temperature) or foreign materials(contamination) and wet chemistry reaction and plasma damage fromBEOL/Packaging processes.

Referring to FIG. 2, a silicon wafer 100 is shown having a plurality ofintegrated circuits (ICs or chips) 104 positioned on a planar surfacearea 102 of the wafer 100. Each of the chips 104 includes a bondingmaterial 108 forming a perimeter on a planar surface area 105 of thechip 104. The wafer 102 also has bonding material 112 forming aperimeter on the planar surface area 102. In the embodiment of theinvention shown in FIG. 2, the bonding material is copper, however,other suitable electrically conductive or non-conductive materials maybe used. It is understood, that the chip and wafer perimeters formed bythe bonding materials 108, 112, respectively, may begin from outer edges106, 101, respectively, and extend radially inwardly from the outeredges along the planar surface areas 105, 102, respectively, of thechips 104 and the wafer 100. Further, the chip and wafers perimetersformed by the bonding materials 108, 112 can also be adjacent, offset,or in spaced adjacency from the outer edges 106, 101, respectively.

The chips 104 also include dummy bonding pads (ads, supportcolumns/pillars) 116 (shown in FIG. 2), which may be made of copper orother suitable materials. The pads or copper pad (supportcolumns/pillars) 116 are structures without any electrical connection,but have a specified position on the planar surface area 105 of the chip104 and a specified height to contact mating pads on a chip (not shown)to be fitted over the chip 104 shown in FIG. 2. The mating pads thenform a structural column or support column (or pillar) in a sealedbonded structure of wafers or separate chips. The mating pads can alsobe bonded together when the wafer of chip is mated, thus forming abonded support column. The mating pads 116 help support the wafer whenstacked with other wafers, as will be discussed herein referring to FIG.3C.

Referring to FIGS. 3A and 3B, a pair of chips 200 are shown in mirrorimage relation. A first chip 200 a and second chip 200 b each haveplanar surface areas 204 a, 204 b, respectively. Bonding materials 206a, 206 b, respectively, define perimeters around the surface areas 204a, 204 b, respectively, on the first and second chips 200 a, 200 b. Asdiscussed in relation to FIG. 2, the bonding material may be cooper, aswell, as other suitable materials. The perimeters defined by the bondingmaterials 206 a, 206 b extend inwardly along the planar surface areas204 a, 204 b, respectively, from outer edges 202 a, 202 b, respectively.

The chips 200 a, 200 b also include dummy bonding pads 208 a, 208 b,respectively (similarly to the chips 104 shown in FIG. 2), which may bemade of copper or other suitable materials as discussed in regard topads 116 on chip 104 in FIG. 2. Similarly to chip 104 shown in FIG. 2,the pads 208 a, 208 b shown in FIG. 3A, 313 are structures without anyelectrical connection, but have a specified position on the planarsurface areas 204 a, 204 b of the chips 200 a, 200 b, respectively. Thebonding pads 212A, 212B may be placed in a geometric pattern, as shownin FIGS. 3A and 3B, but also may be placed in any pattern, ornon-pattern desired, or in any quantity desired.

Each of the pads 208 a on chip 200 a have a specified height to contactmating pads 208 b on chip 200 b when the chips 200 a, 200 b are placedin overlapping relation and bonded as shown in FIG. 3C. The pads 208 a,208 b coupled (or bonded or fused) together form mated pads 220 orstructural columns, show in FIG. 3C, in the bonded chip structure 250,as shown in FIG. 3C. Further, the bonded chip structure 250 comprises abonded perimeter 216 consisting of bonding material 206 a and bondingmaterial 206 b mated together. In the bonded chip 250 (shown in FIG.3C), the bonding material 206 a, 206 b shown in FIGS. 3A and 3B areaffixed together to form a seal 216 around the perimeter of the bondedchip 250. The forming of the seal 216 includes compressing the bondingmaterial together and heating the bonding material. Other methods offorming the seal are also contemplated and within the scope of thepresent invention. The seal 216 stops unwanted entry of, for example,materials, substances, or debris into the bonded chip 250, i.e., betweenthe chips 300 a and 300 b.

Referring to FIG. 3C, the wafers 200 a, 200 b are shown bonded togetheras a bonded chip structure 250, in cross-section, so that the mated padsor structural columns 220 are shown. The mated pads or structuralcolumns 220 are the pads (or dummy pads) 212 a on first wafer 200 a andsecond wafer 200 b mated together. The dummy pads mated together to formstructural columns 220 provide strength to the bonded wafer 250. Thepads 220 help support the surface areas 204 a and 204 b of the first andsecond wafers 200 a, 200 b, respectively. The surface areas 204 a, 204 bhave an inherent weight, and thus there are axial forces 252 across thesurface areas 204 a, 204 b perpendicular to the “X” axis 253 a and alongthe “Y” axis 253 b. More particularly, the axial forces 252 are from,for example, the inherent weight of the surface areas 204 a, 204 b ofthe first and second wafers 200 a, 200 b due to gravitation forces, oraxial force (or pressure) from the weight of other chips (or wafers)stacked on the bonded chip 250. The structural columns 220 providesupport along the surface areas 204 a, 204 b of the first and secondchips 200 a, 200 b, respectively, to support the axial forces. Morespecifically, when additional chips are stacked over each other,additional axial forces from the weight of additional chips bear down(along the “Y” axis 253 b) on the outer top surface 256 of the bondedwafer 250. Further, the mated pads/structural columns 220 help tostabilize the bonded wafer 250 against torsional forces (or stresses),which may occur in the processing or fabricating of the wafer or fromdisproportionate weight distribution from stacking other chips (orwafers) over one another such that twisting or bending occurs along thesurface areas 204 a, 204 b of the chips 200 a, 200 b. If torsionalstresses are applied to the bonded chip 250, the torsion causes twistingof the bonded chip 250 that may result in shearing stress which areperpendicular to surface areas 204 a, 204 b (in the “Y” direction 253b). Thus, in one example, the structural columns may be positioned onthe surface area of a chip or wafer in an area unpopulated by othercomponents to effectively distribute axial and torsional forcesthroughout the chip or wafer during processing. Distribution of forcesthroughout the chip or wafer lessens the force in one particular areaand thereby reduces the stress in that area lessening the likelihood ofa stress related fracture or break in the chip or wafer structure. Also,the support columns reduce possible stresses from torsion and axialloads on the seal. Further, an uncompromised seal (preferably a hermeticseal) about each chip or wafer prevents, for example, liquid and gasetchants/corrosives and particulate materials from ingressing into areaswhich will be damaged by such ingress.

It is understood that a chip or wafer may have multiple electricalreference layers connected by vertical vias (not shown). The dummy pads,for example, as described in relation to FIGS. 3A-3C, can be positionedbetween layers in the chip or wafer to provide support between thelayers, as well as providing support between the chips or wafersthemselves.

Referring to FIGS. 4A and 4B, wafers 300 a, 300 b, respectively, includea plurality of chips 304 positioned on surface areas 302 a, 302 b. Thesurface areas of the wafers 300 a, 300 b include bonding material 312forming a perimeter around the wafers 300 a, 300 b with a thickness 320(shown in FIG. 4D) starting from the edge of the wafers 301 a, 301 b andextending inwardly on the surface areas 302 a, 302 b of the wafers 300a, 300 b. The chips 304 on the surface areas 302 a, 302 b of the wafers300 a, 300 b include dummy pads 208 a, 208 b as depicted in more detailin FIGS. 3A and 313, and described above. Further, the chips 304 onwafers 300 a, 300 b include bonding material 206 a, 206 b, respectively,defining a perimeter around the chip 304 as shown in more detail inFIGS. 3A and 3B, and described above.

Wafers 300 a and 300 b are combined by positioning one wafer over theother to form bonded wafer 350, shown in FIG. 4C. In the bonded wafer350, the bonding material 312 shown in FIGS. 4A and 4B are affixedtogether to form a seal 312 around the perimeter of the bonded wafer350. The forming of the seal includes compressing the bonding material312 between the wafers 300 a, 300 b and heating the bonding material 312to form the bonded seal 316. The bonded seal 316 stops unwanted entry offor example, materials, substances, or debris into the bonded wafer 350,i.e., between the wafers 300 a and 300 b.

Referring to FIG. 4D, a cross-section of the combined wafers 350 isshown along line X-X to show the bonded seal 316, resulting from bondingtogether of bonding material 312 on each wafer 300 a, 300 b, extendinginwardly from the edges 301 a and 301 b of the wafers 300 a, 300 b. Thebonded seal 316 around the perimeter of the wafer 350 is shown in FIG.4D.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that changes in forms and details may be madewithout departing from the spirit and scope of the present application.It is therefore intended that the present invention not be limited tothe exact forms and details described and illustrated herein, but fallswithin the scope of the appended claims.

1-6. (canceled)
 7. A method for sealing a microelectronic structure andproviding mechanical stress endurance, comprising: providing andpositioning a plurality of chips on at least two wafers beingelectrically connected to a semiconductor structure at a plurality oflocations, the chips comprising outer edges; depositing a length ofcontinuous bonding material on each chip on a planar surface thereofdefining a perimeter substantially adjacent to the outer edge of eachchip; connecting at least one support column on each of the chips andwithin the perimeter of each chip, each support column extendingoutwardly; positioning the chips in overlapping relation such that thebonding material and the support columns are in mating relation to eachother, respectively; compressing the chips and thereby the bondingmaterial together; heating the bonding material to form a seal about theperimeter of the chips whereby a bonded chip structure is formed;positioning a plurality of support columns between multiple layers inthe chips to provide support between the layers; depositing a bondingmaterial along a perimeter adjacent to an outer edge of the wafer;compressing the bonding material on each of the wafers together witheach other in mating relation; and heating the mated bonding material toform a seal and a bonded wafer structure.
 8. (canceled)
 9. (canceled)